Introduction

In last week's blog post we found out why the specify blocks were missing from the PDK. The reason is that they were simply omitted when building the PDK via open_pdks.

This week I tried to include these specify blocks in the PDK and simulate them with Icarus Verilog.

Icarus Verilog already supports IOPATH delays, i.e. delays within the module from an input to an output, so at least this part should work in the simulation. But after I set everything up and started the simulation, the dfrtp cell (which I had looked at) only gave an x at the output. What went wrong?

Delayed Signals

It turns out that parsing the specify blocks is not a problem at all, but that there is another issue with $recrem and $sethuphold: to support negative timing checks, these directives should generate delayed signals of the reference_event and data_event.

$recrem ( posedge RESET_B , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , CLK_delayed ) ;
$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ;
$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ;

Icarus Verilog does not support this yet, which is reflected in warnings like this one:

sky130_fd_sc_hd.v:106606: warning: Timing checks are not supported and delayed signal "CLK_delayed" will not be driven.

But the problem is that these delayed signals are needed in order for the model to work at all. For now, I've worked around this problem by assigning these signals manually:

assign RESET_B_delayed = RESET_B;
assign CLK_delayed = CLK;
assign D_delayed = D;

With these changes, I was able to correctly annotate the rise/fall times for the output of this model. But of course, this is just a workaround.

Timing checks are a big subject in themselves, and I don't think it would make sense to work on implementing $recrem and $setuphold now as well.

But for now there is another solution. Section "15.5.4 Option behavior" in the standard says the following:

As already mentioned, the ability of Verilog simulators to handle negative values in $setuphold and $recrem timing checks shall be enabled with an invocation option. It is possible models written to accept negative timing check values with delayed reference and/or delayed data signals can be run without this invocation option enabled. In this circumstance, the delayed reference and data signals become copies of the original reference and data signals. The same occurs if an invocation option turning off all timing checks is used.

That is, the right thing for the simulator to do when timing checks are disabled (or not supported as in our case) is for the delayed signals to simply become copies of the originals.

This means that what I did manually with the assignments, the simulator should do automatically.

Summary

In summary, this means I have one more task on my list, but this one seems to be relatively simple and a good start for my first feature implementation. Thus I will be working on it right away!